This invention relates to integrated circuits and, more particularly, to functional testing and debugging of integrated circuit designs.
The 10/956,854 patent application discloses a beneficial design approach for System on a Chip (SoC) devices, where each core is encompassed with a wrapper that includes a functionally reconfigurable module (FRM). The advance in the art disclosed in the 10/956,854 patent application incorporates configurable circuits within the FRM that perform assertion checking.
In assertion checking, a collection of conditions is identified which conditions are expected to hold true during the operation of a properly working SoC. To perform assertion checking, the tested SoC receives various input test vectors, and the resulting SoC states are checked against a collection of assertions. Assertion checking can be of two types: “at-speed” assertion checking, and “single-step” assertion checking. In at-speed assertion checking all of the inputs and outputs of a core are available, in parallel, to the assertion checking circuitry within the FRM. The logic for performing the assertion checking is responsive to some or all of these signals, and this logic operates in parallel. In single-step assertion, the internal flip-flops of the SoC are connected to form a scan chain (the circuitry for forming the scan chain having been included in the SoC design in accord with conventional design practices), the data of the formed scan chain is clocked out, and the information thus obtained is analyzed to determine whether any of the assertions fire.
The 10/956,854 patent application also disclosed the Continuous Single Step (CSS) mode, which makes possible automatic checking such assertions after every functional clock. That is, the SoC under test is activated in its normal mode (mode A) for a single period of the operational clock, and then moved to its assertion checking mode (mode B). During the assertion checking mode the scan chain is formed, the data are outputted and captured (and reinserted, to return the circuit to its operational state), and tested against the set of assertions. If none of the assertions fires, the SoC is again activated in its normal state for one period of the operations clock, and then again moved to its assertion checking mode.
FIG. 1 shows a core 20 of an SoC and its associated FRM 30. Core 20 is shown to receive two control signals from a management circuit (not shown), one of which configures the flip-flops within core 20 into a chain scan (as depicted in the FIG.), and the other provides a clock. The clock signal causes the states of the flip-flops to appear at the SO output, and those states applied to both the SI input and bit extractor 52. The duration of the clock is set to restore core 20 to the state it was in before commencement of the clock.
It should be understood that a core can be designed to comprise more than one scan chain, with a plurality of SO outputs and SI inputs, although FIG. 1 shows only one scan chain for sake of simplicity. It should be further understood in the context of this disclosure that although one scan chain is shown, as well as one bit extractor and one set of circuits responsive to the bit extractor, in FIG. 1 as well as in subsequent FIGS. a plurality of scan chains might be employed, in which case a plurality of bit extractors and corresponding subsequent circuits would also be employed. It is noted that a plurality of bit extractors can be combined to form a single bit extractor with a plurality of outputs, and it is also noted that a plurality of scan chains can be outputted via a single output terminal of a core, thus effectively outputting the various scan chains in a seriatim manner. In such a case, a single bit extractor may suffice.
As for the structure of bit extractor 32, skilled artisans would recognize that there are numerous ways to implement a bit extractor. One very simple way is to configure an addressable memory that stores the numbers of the identified sequence; for example, the memory might be uploaded with the values 5, 28, . . . 111. Within the bit extractor there might be a counter A that advances with each test clock, a counter B that addresses the memory, and a comparator responsive to the output of the memory and to counter A. Thus, when the first entry of the memory is retrieved (e.g., 5), the comparator fires when counter A reaches the value 5, indicating that the fifth bit of the scan chain is available, at which time the available bit is presented to the output of bit extractor 32. At that time counter B is incremented, advancing the address and causing the memory to output its second entry, i.e., 28. The process continues until the 28th bit arrives and it is outputted, etc.
Under control of bit extractor logic 32, selected bits of the Scan Output (SO) are stored in register 34. Those bits are applied to Assertion Logic (AL) circuits 35-1 through 35-K, each of which checks one assertion. The outputs of the AL circuits are stored in respective flip-flops 36-1 through 36-K, and those flip-flops are interconnected to provide a serial output of their contents to the management circuit. The serial output of register 34 is connected to flip-flop 36-1, which allows the management circuit to receive and additionally analyze the bits collected by extractor logic 32. Finally, the outputs of the AL circuits are also applied to OR gate 37 that provides an indication to the management circuit as to whether any of the assertions fired. Of course, the management circuit includes means to output various signals to the user who is exercising the SoC and means to stop the functional clock when an assertion fires. The management circuit is not shown because its design depends on the particular choices that may be made in connection with specific SoCs, or in connection with the goals set for simulating an SoC, and such designs do not form a part of this invention. However, it should be realized that both in connection with the FIG. 1 circuit in connection with the other FIGS. a management circuit is included for controlling operation of the circuits embodying the concepts of this invention and for outputting results of the assertion checking.
There are significant advantages to circuit disclosed in FIG. 1, but it is noted that the assertion logic circuits operate in parallel, therefore the amount of logic they require depends of the number of extracted bits and these circuits potentially can take up a significant amount of FRM “real estate.”